The present invention relates to a method for fabricating a semiconductor device.
In recent years, rapid miniaturization in the field of semiconductor devices has spurred the trends toward higher-speed operation and lower power consumption. However, conventional processes using bulk silicon wafers are approaching their limits in terms of achieving higher-speed operation and lower power consumption. On the other hand, there have been growing expectations for processes using silicon-on-insulator (hereinafter referred to as SOI) wafers as next-generation devices.
In a process using a SOI device, such as a MOS transistor, formed on a SOI wafer, emphasis has been placed on compatibility with a process using bulk silicon.
FIGS. 11A and 11B and FIGS. 12A and 12B are cross-sectional views illustrating the process steps of fabricating a conventional SOI device.
First, in the step shown in FIG. 11A, a buried oxide film layer (BOX layer) 101 is formed by a method of implanting oxygen ions into a region at a given depth from a surface of a Si substrate 100 or the like. Then, a Si layer 102 is formed on the BOX layer 101. After an oxide film 103 and a silicon nitride film 104 are grown on the Si layer 102, the oxide film 103 and the silicon nitride film 104 are patterned by lithography and dry etching so that openings are formed in isolation regions 105.
Next, in the step shown in FIG. 11B, the Si layer 102 is patterned by dry etching by using the silicon nitride film 104 as a mask so that transistor regions 102a each composed of the Si layer are formed, while trenches 106 are formed simultaneously in the isolation regions 105.
Next, in the step shown in FIG. 12A, the side surfaces of the transistor region 102a are oxidized so that sidewall oxide films 107 are formed. At the same time as the formation of the sidewall oxide films 107, the edge portions of the upper surfaces of the transistor regions 102a are rounded off so that the localization of an electric field to the edge portions is suppressed.
Then, in the step shown in FIG. 12B, CVD oxide films are buried in the trenches 106 to form buried shallow trench isolations 110 (hereinafter referred to as STIs).
However, the conventional SOI device has the following problems.
When the sidewall oxide films 107 are formed in the step shown in FIG. 12A, the lower-surface edge portions of the transistor regions 102a in contact with the BOX layer 101 are significantly oxidized. At this time, the transistor regions 102a are oxidized not only by oxygen passing through the sidewall oxide films 107 but also by oxygen passing through the BOX layer 101, so that abnormal oxide regions 109 are formed. This warps the lower-surface edge regions of the transistor regions 102a upward and deforms the substrate. Consequently, a failure occurs in the portion of the transistor regions 102a on which the stress of deformation is exerted and malfunction or a leakage current resulting from the failure may occur.
However, if an amount of oxidation is reduced for the suppression of abnormal oxidation of the lower-surface edge regions of the transistor regions 102a as described above, the upper-surface edge portions of the transistor regions 102a cannot be rounded off satisfactorily. This causes the localization of an electric field to the upper-surface edge portions. In the subsequent step, the problem of a reduction in threshold voltage may occur due to partial destruction of a gate oxide film.